Method and system for drift reduction in a low power oscillator (lpo) utilized in a wireless communication device

ABSTRACT

A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

Not applicable

FIELD OF THE INVENTION

Certain embodiments of the invention relate to communication devices.More specifically, certain embodiments of the invention relate to amethod and system for drift reduction in a low power oscillator (LPO)utilized in a wireless communication device.

BACKGROUND OF THE INVENTION

In recent years, there has been a phenomenal growth in mobile orhandheld computing and communication devices such as, for example,personal digital assistants (PDAs), mobile phones, smart phones andpersonal media players. As these devices increasingly becomeindispensable, multiple usage scenarios via various wirelesstechnologies have resulted in users gravitating toward these devices.For example, multiple technologies such as wireless WAN (cellular orWiMAX), high-speed wireless LAN (WiFi), short-range wireless(Bluetooth), GPS, FM and mobile TV, which are integrated within a devicemay enable a user of a device to make phone calls, download songs,listen through headsets, check location, listen to talk shows and/orwatch sportscasts. In certain circumstances, some of these technologiesmay operate at the same time. Device vendors are then faced with thetask of balancing the need for more features in these devices tooptimize user experiences and/or productivity, with the conflictingforces of lower cost, smaller device sizes and longer battery life.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with the present invention as set forth inthe remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for a method and system for drift reduction in alow power oscillator (LPO) utilized in a wireless communication device,substantially as shown in and/or described in connection with at leastone of the figures, as set forth more completely in the claims.

Various advantages, aspects and novel features of the present invention,as well as details of an illustrated embodiment thereof, will be morefully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an exemplary system forregulating sleep intervals for a high frequency crystal oscillatordriven circuit, in accordance with an embodiment of the invention.

FIG. 2 is a timing diagram illustrating exemplary LPO calibration andadjustment time intervals as well as frequency drift for an LPO, inaccordance with an embodiment of the invention.

FIG. 3 is a timing diagram illustrating an exemplary two pointcalibration for reducing a time interval for radio circuit activityand/or events, in accordance with an embodiment of the invention.

FIG. 4A is a timing diagram illustrating a multipoint calibration thatresults in a delay of radio circuit activity, in accordance with anembodiment of the invention.

FIG. 4B is a timing diagram illustrating a multipoint calibration thatadvances radio circuit activity to an earlier time, in accordance withan embodiment of the invention.

FIG. 5 is a flow chart illustrating exemplary steps for reducing a timeinterval utilized for driving a circuit with a high frequency crystaloscillator, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor drift reduction in a low power oscillator (LPO) utilized in awireless communication device. Various communication devices, forexample, a Bluetooth, cellular, WIMAX, GPS, near field communication(NFC) and/or Zigbee device may utilize two oscillators, a first one thatmay be more accurate and more spectrally pure such as a high frequencycrystal oscillator (HFCXO), and a second one that may be less accurateand less spectrally pure and may utilize less power to operate such as alow power oscillator (LPO). The term “high frequency oscillator” may beutilized in place of “high frequency crystal oscillator (HFCXO)” and theterm “low frequency oscillator” may be utilized in place of “low poweroscillator (LPO). The low power oscillator (LPO) may be utilized fordigital processing tasks which may not require the high performanceprovided by the HFCXO. In various embodiments of the invention, circuitsdriven by the HFCXO, for example radio circuits, may sleep in betweenperiods of activity in order to reduce power consumption. Time intervalsfor circuits to sleep and/or wake up may be regulated by the LPO whichmay be, for example, a 32 KHz LPO.

Exemplary aspects of the invention may enable an LPO to realize a moreaccurate time at which to wake-up and utilize the HFCXO as a highfrequency and/or accurate timing source. In this regard, a sleep timeinterval for a circuit which may be driven by the HFCXO may be adjustedbased on a detected frequency drift in the LPO. For example, the sleeptime interval may be adjusted for the circuit while the HFCXO is drivenby the LPO. In various embodiments of the invention, the LPO may becalibrated based on an output of the HFCXO. The LPO frequency drift maybe detected based on a first frequency sampled at a first time instantand a second frequency sampled at a second time instant, and a timeinterval between the first and second time instants. In addition, thefirst time instant may occur after a first LPO calibration and thesecond time instant may occur after a second LPO calibration.Furthermore, the first time instant may occur after a first LPO clockadjustment which may occur after the first LPO calibration. The detectedLPO frequency drift may be utilized to determine a time interval foradjusting the HFCXO sleep time interval. In this regard, the determinedtime interval may be based on two or more LPO calibrations and/or one ormore LPO clock adjustments. The sleep time interval may be increased byadding a time delay to an expected time to wake the HFCXO and/or theHFCXO driven circuit. Also, the HFCXO and/or the HFCXO driven circuitsleep time interval may be decreased by subtracting a time interval fromthe expected wake time. According to an embodiment of the invention, thecircuit driven by the HFCXO may be a radio circuit. The radio circuitmay be enabled to perform various tasks more quickly in instances whenthe time to wake the HFCXO circuit is more accurate due to the two ormore calibrations between sleep and wake cycles.

FIG. 1 is a block diagram illustrating an exemplary system forregulating sleep intervals for a high frequency crystal oscillatordriven circuit, in accordance with an embodiment of the invention.Referring to FIG. 1, there is shown a system 100 that comprises a lowpower oscillator (LPO) 110, an LPO clock 112, a high frequency crystaloscillator (CXO) 114, a high frequency crystal oscillator (HFCXO) clock116, a circuit 118, a processor 120 and a memory 122.

The system 100 may comprise a portion of a wireless device, for example,a Bluetooth, cellular, WIMAX, GPS, NFC and/or Zigbee device. In variousembodiments of the invention, various elements of the system 100 may belocated on different devices. For example, the LPO 110 may be located onan inexpensive Bluetooth device while the HFCXO 116 may be located on acommunicatively coupled mobile phone.

The low power oscillator (LPO) 110 may comprise suitable logic circuitryand/or code that may be operable to generate timing signals forregulating sleep and wake state intervals for one or more circuits suchas the circuit 118. In addition, the LPO 110 may be utilized to drivevarious clocks for regulating various digital processing functionswithin the system 100. The LPO 110 may be, for example, a 32 kHz crystaloscillator that may be somewhat noisy and may easily drift in frequency.The LPO 110 may be calibrated based on input signals from the HSCXOclock 116.

The LPO clock 112 may comprise suitable logic, circuitry and/or codethat may be operable to generate clock output signals based on inputfrom the LPO 110. The generated clock signals may regulate timeintervals for sleep and wake states for one or more circuits such as thecircuit 118. Timing of the LPO clock 112 output signals may becalibrated and/or adjusted based input from the HFCXO 116 and/or theprocessor 120. In addition, the LPO clock 112 may be enabled to delay oradvance to an earlier time, the sleep and/or wake intervals for the oneor more circuits such as the circuit 118. The LPO clock 112 maycommunicate frequency and/or timing information that may enabledetermination of delay and/or advanced wake times. For example afrequency of the LPO clock 112 output after a first timing adjustmentand/or a frequency of the LPO clock 112 output before a second timingadjustment may be communicated to the processor 120 and/or memory 122.

The high frequency crystal oscillator (HFCXO) 114 may comprise suitablelogic, circuitry and/or code to generate a time reference for one ormore circuits requiring high frequency, accurate timing signals. Forexample, the HFCXO 114 may be utilized to drive a clock such as theHFCXO clock 116 that may drive the circuit 118. In this regard, the highfrequency CXO 114 may enable radio communication. In addition, the HFCXO114 may generate a time reference for calibrating the LPO 110. The HFCXO114 may provide a higher level of accuracy and/or spectral purity thanthe LPO 110 however; it may require a higher level of current than theLPO 110 to operate. Therefore, energy may be conserved in the system 100by utilizing the LPO 110 and/or turning off the HFCXO 114 for tasksand/or circuits that do not require such a high level of performance.Time intervals during which the HFCXO 114 is off and/or on may bereferred to as sleep and/or wake cycles.

The high frequency crystal oscillator (HFCXO) clock 116 may comprisesuitable logic circuitry and/or code that may be operable to generatetiming signals for the circuit 118 and/or the LPO 110 based on a timereference from the HFCXO 114. For example, the HFCXO clock 116 may drivethe circuit 118 which may comprise a radio frequency circuit and/or maysupport Bluetooth communications for example. In addition, the HFCXOclock 116 output may be utilized for calibration of the LPO 110 and fordetermining LPO clock 112 timing adjustments.

The circuit 118 may comprise suitable logic circuitry and/or code thatmay be operable to process and or communicate data based on clocksignals from the HFCXO clock 116 output. For example, the circuit 118may require and/or utilize high frequency, spectrally pure signals fromthe HFCXO clock 116. In this regard, the circuit 118 may be an RFcircuit that may utilize, for example, Bluetooth, cellular, WIMAX, GPS,NFC, Zigbee and/or other wireless technologies to communicate.

The processor 120 may comprise suitable logic circuitry and/or code thatmay be operable to determine sleep and/or wake time intervals fordriving the circuit 118 by the HFCXO 114 and/or the HFCXO clock 116 andmay compensate for frequency drift in the LPO 110 and/or LPO clock 112.Accordingly, the processor 120 may receive frequency and/or timeinformation about the LPO 110 and/or LPO clock 112 one or morecalibrations of the LPO 110. The processor 120 may approximate thefrequency drift of the LPO 110 and may compensate for the drift. Forexample, the processor 120 may determine a time interval (ΔT) that maybe added to or subtracted from an expected time interval (T) for wakingup the circuit 118. Compensating for frequency drift in the LPO 110 withthe added ΔT may enable the circuit 118 to sleep longer and wake up at amore accurate time which may reduce time needed for the circuit 118 towake up. A reduction in wake time for the HFCXO 114 and circuit 118 mayenable significant power savings. For example, the circuit 118 may needan interval on the order of microseconds to accomplish a task; however,a timing uncertainty on the order of a millisecond may be introduced dueto the frequency drift. In addition, the processor 120 may managevarious other functions for the system 100.

In various embodiments of the invention, the processor 120 may beoperable to detect and/or estimate a frequency drift in the LPO 110and/or the LPO clock 112 based on one or more attributes of and/or oneor more measurements taken within the system 100. For example,variations in a voltage level and/or a temperature level may be utilizedto detect a frequency drift.

The memory 122 may comprise suitable logic, circuitry and/or code thatmay be operable to store frequency and/or timing data for the system100. In addition, the memory 122 may store instructions for determiningthe sleep and/or wake time intervals as well as for calibration and/ortiming adjustments for the LPO 110 and/or LPO clock 112. The memory 122may store additional information to support system 100 operations.

In operation, the circuit 118 may be for example, an RF circuit 118 thatmay be driven by the HFCXO clock 116. The circuit 118 and/or HFCXO 114may wake up to perform 1 or more tasks, for example, to search for abeacon signal that may begin at a specified time, and then may go backto sleep. It may be beneficial to reduce the wake time duration, forexample, to conserve energy. The LPO 110 and/or LPO clock 112 mayregulate the sleep and wake cycles of the HFCXO 114 and/or the circuit118. The LPO 110 may experience significant frequency drift which mayintroduce timing uncertainties. The duration of a sleep cycle may be onthe order of a second, for example. Due to timing uncertainties, thewake cycle duration may vary on the order of 1 millisecond to 1microsecond for example. In various embodiments of the invention, asleep and/or wake cycle duration may comprise an expected duration T andan added or subtracted sleep time ΔT wherein ΔT may compensate for thefrequency drift and may reduce the timing uncertainty. The processor 120may determine ΔT.

The determination of ΔT may utilize information derived from two or morecalibrations and/or timing adjustments of the LPO 110 and/or LPO clock112. For example, a difference in frequency taken just after a firstcalibrated timing adjustment f₁ and just after a subsequent calibrationf₂ may enable approximation of the frequency drift over a known durationof time T. In accordance with an embodiment of the invention, ΔT may bedetermined based on the following expression.

ΔT=T(f ₂ −f ₁)

where f₁ may be a calibrated and/or corrected frequency at a time priorto a frequency drift, f₂ is a frequency measured after the frequencydrift, T may be a time interval and/or number of clock cycles between f₁and f₂ and ΔT may be a timing error due to the frequency drift, forexample, a time interval and/or a number of LPO clock cycles. Forexample, in instances where the LPO 110 frequency may be too high, theLPO clock 112 may wait an additional interval ΔT clock cycles after timeinterval T before waking the RF circuit 118. The invention is notlimited to any specific method for approximating the frequency drift andany suitable method may be utilized. For example any suitable linearapproximation and/or a polynomial approximation may be utilized.

FIG. 2 is a timing diagram illustrating exemplary LPO calibration andadjustment time intervals as well as frequency drift for an LPO, inaccordance with an embodiment of the invention. Referring to FIG. 2,there is shown four timelines 210, 212, 214 and 216 that indicateexemplary relative times for activity and/or events within the system100.

In timeline 212 there is shown a sequence of time intervals during whichthe LPO 110 may be calibrated based on input from the HFCXO clock 116.In timeline 210 there is shown a sequence of time intervals during whichthe LPO clock 112 timing may be adjusted based on a recent calibrationof the LPO 110 shown in timeline 212. For example, after eachcalibration of the LPO 110, the LPO clock 112 timing may be adjusted. Intimeline 214 there is shown the output of the LPO clock 112 that may beupdated based on a most recent calibrated timing adjustment shown intimeline 210.

In time line 216, there is shown frequency drift in the LPO 110 relativeto the calibration and timing adjustments shown in time lines 210 and212. In this regard, the timeline 216 indicates that the frequency driftis at a low point at a time instant just after the LPO clock 112receives a calibrated timing adjustment and the frequency correspondingto that low point is labeled f₁. In between the first calibrated timingadjustment and the second calibrated timing adjustment, the frequencydrifts to a high point. The frequency determined at the highpoint of thefrequency drift is labeled f₂. Also, a time interval T is indicated thatspans the time between the f₁ and f₂. Frequency values corresponding tof₁, f₂ and the time interval T may be utilized to determine a timeinterval ΔT as described with respect to FIG. 1. Notwithstanding therelative time intervals shown in FIG. 2, in various embodiments of theinvention, two or more active intervals shown in FIG. 2 may overlap intime.

FIG. 3 is a timing diagram illustrating an exemplary two pointcalibration for reducing a time interval for radio circuit activity, inaccordance with an embodiment of the invention. Referring to FIG. 3there is shown two timelines 310 and 312. The timeline 312 shows the LPOclock 112 timing output as described with respect to FIG. 2.

The timeline 310 shows a plurality of events that may enable sleepand/or wake cycles for the circuit 118 and HFCXO 114. In timeline 310,following the first calibration and timing adjustment that weredescribed with respect to FIG. 2, the low point frequency f₁ may bestored in the memory 122. At a time instant near the first LPO clockadjustment, the HFCXO 114 may be engaged and the HFCXO clock 116 outputmay drive the circuit 118. The circuit 118 may be awake for a specifiedinterval of time that may comprise a large uncertainty and may be turnedoff when circuit 118 tasks are finished. At or near the end of the timeinterval T when the frequency drift may be at a high point, the HFCXO114 may be turned on to calibrate the LPO 110 and to determine f₂ andthe HFCXO 114 may be turned off. A value for ΔT may be determined basedon f₁, f₂ and T as described with respect to FIG. 2. The timing of theLPO clock 112 output may be adjusted to output LPO₂.

After the adjustment, the LPO clock 112 output may again be at low levelof frequency drift and the system may record f₃. The LPO clock 112 mayreduce the timing uncertainty by waiting the time interval ΔT beforeawakening the HFCXO 114. Once the HFCXO 114 is awake, the HFCXO 116 maydrive the wake cycle of the circuit 118. In this manner, the circuit 118wake cycle may be shortened due to the reduced timing uncertainty. Forexample, in instances where the circuit 118 may be an RF circuit, thetiming uncertainty may be reduced and the timing reference for thecircuit 118 may be more accurate. In this regard, the circuit 118 maynot need to wake up early to search for signals and determine timing andmay be able to finish its tasks over a shortened interval of time.Notwithstanding the order of active time intervals and/or events shownin FIG. 3, in various embodiments of the invention, two or more of theactive intervals shown in FIG. 3 may overlap in time.

FIG. 4A is a timing diagram illustrating a multipoint calibration thatresults in a delay of radio circuit activity, in accordance with anembodiment of the invention. Referring to FIG. 4A, there is shown a timeline comprising events and/or active time intervals. The first LPO 110calibration, first LPO clock 112 timing adjustment and first circuit 118active interval are similar and/or substantially the same as thosedescribed with respect to timeline 310 shown in FIG. 3. Referring toFIG. 4A, there may be a long time interval between a first circuit 118active period and the second circuit 118 active period. In addition,there may be multiple calibrated timing adjustments and multiple timeintervals T in between the first and second circuit 118 active periods.For example, there are four time interval Ts shown in FIG. 4A. A timeinterval, ΔT, may be determined after each LPO 110 calibration. The ΔT'smay be accumulated and a net ΔT may be determined. Furthermore, a timeinterval, ΔT and/or a corresponding frequency drift may be determinedbased on a plurality of prior LPO 110 calibrations. In instances where afrequency of the LPO 110 may have increased over the span of T1 throughT4, it may be determined by the processor 120 that the LPO clock 112 mayhave run too fast and a time delay based on the sum of all four ΔTs maybe added after the last time interval T₄.

Aspects of the invention may comprise various methods of schedulingand/or triggering of the LPO 110 calibrations and/or LPO clock 112adjustments. A state machine may control when an LPO 110 calibrationand/or LPO clock 112 adjustment may occur. In various embodiments of theinvention, LPO 110 calibrations and/or LPO clock 112 adjustments may betriggered based on a determined frequency error or calibration results.For example, in instances when ΔT₁ may be comprise a short duration orthe frequency error may be small, a second or third LPO 110 calibrationand/or LPO clock 112 adjustment may be skipped or may be scheduled at alater time. In this regard, a small amount of frequency drift may resultin fewer calibrations and/or adjustments between wake time intervalsand/or a greater amount of frequency drift may result in a greaternumber of calibrations and/or adjustments between wake time intervals.Furthermore, one or more LPO 110 calibrations may occur without acorresponding LPO clock 112 adjustment. For example, the LPO clock 112may be adjusted after a plurality of LPO 110 calibrations or the LPOclock 112 may not be adjusted at all.

FIG. 4B is a timing diagram illustrating a multipoint calibration thatadvances radio circuit activity to an earlier time, in accordance withan embodiment of the invention. Referring to FIG. 4B there is shown atime line comprising events and/or active time intervals similar to theevents and/or time intervals described with respect to FIG. 4A. However,in FIG. 4B, frequency of the LPO 110 may have slowed down instead ofspeeding up. By the end of time interval T3, it may be determined thatthe LPO clock 112 may have been running too slow. The processor 120 maydetermine that it should not wait until the end of T4 to turn on thecircuit 118 and may forego the last set of LPO 110 calibration and LPOclock 112 timing adjustment shown in FIG. 4A. In this manner, theprocessor 120 may determine that a time interval determined based on anaccumulation of the first three ΔTs may be subtracted from the timeinterval T₄ and that activation of the circuit 118 may occur prior tothe end of the expected interval T₄.

FIG. 5 is a flow chart illustrating exemplary steps for reducing a timeinterval utilized for driving a circuit with a crystal oscillator, inaccordance with an embodiment of the invention. Referring to FIG. 5exemplary steps may begin at step 502. In step 504, based on timing froma low power oscillator (LPO) clock 112 output LPO₀, engage the highfrequency crystal oscillator (HFCXO) 114, calibrate LPO 110 with theHFCXO 114 and/or HFCXO 116 and turn off HFCXO 114.

In step 506, based on the calibration of the LPO 110, adjust LPO₀ clockoutput to LPO₁. In step 508, based on LPO₁, drive an RF circuit 118 withan HFCXO clock 116 output until RF circuit 118 tasks are complete and/orfor a specified time interval. In step 510, based on the LPO₁ clockoutput, the RF circuit 118 may sleep for a specified time interval T. Instep 512, prior to the end of the RF circuit 118 sleep time interval;the HFCXO 114 and/or HFCXO clock 116 may be engaged to calibrate the LPO110 again. In step 514, based on the second LPO 110 calibration, adjustthe LPO clock 112 output from LPO₁ to LPO₂. In step 516, a ΔT may bedetermined and based on the determined delta ΔT, wait beyond the timeinterval T or start early to wake up the HFCXO 114 and or HFCXO clock116 and drive the RF circuit 118 with the HFCXO 114 and/or HFCXO clock116 for a shortened period of time. Step 518 may be an end of exemplarysteps.

In an embodiment of the invention, sleep time intervals between periodsof activity may be increased in a circuit 118 that may be driven by aHFCXO 114 and/or HFCXO clock 116. Increasing the sleep time intervalsbetween periods of activity may reduce a timing uncertainty in a waketime interval for the HFCXO 114 driven circuit 118. LPO 110 may regulatethe sleep time intervals. Compensation may be made for frequency driftin the LPO 110. Frequency drift compensation may be determined based onan LPO 110 first frequency (f1) known at a first time instant and asecond LPO 110 frequency (f2) known at a second time instant and a timeinterval (T) between the first time instant and the second time instant.In this manner, the first time instant may occur after a firstcalibration of the LPO 110 and corresponding LPO clock 112 adjustmentand the second time instant may occur after a second calibration of theLPO 110. Moreover, a time interval that may be utilized to increase thesleep time intervals may be determined based on the first frequency f₁,second frequency f₂ and the time interval T. The LPO 110 may becalibrated based on the HFCXO 114 output. Two or more LPO 110calibrations and/or LPO clock 112 adjustments may be utilized todetermine the frequency drift compensation for increasing the sleep timeintervals. The sleep time intervals may be increased by adding and/orsubtracting the time interval to an expected time to wake the HFCXO 114and/or the circuit 118 driven by the HFCXO 114 and/or HFCXO clock 116.According to an embodiment of the invention, the circuit driven by thehigh frequency crystal oscillator 114 may be a radio circuit.

In another embodiment of the invention, aspects of the invention mayenable a low frequency oscillator 110 to realize a more accurate time atwhich to wake-up a high frequency and/or accurate timing source 114. Inthis regard, a sleep time interval for a circuit 118 which may be drivenby the high frequency oscillator 114 may be adjusted based on a detectedfrequency drift in the low frequency oscillator 110. For example, thesleep time interval may be adjusted for the circuit 118 while the highfrequency oscillator 114 is driven by the high frequency oscillator 114.

In various embodiments of the invention, the high frequency oscillator114 may be calibrated a based on an output of the high frequencyoscillator 114. The high frequency oscillator 114 frequency drift may bedetected based on a first frequency sampled at a first time instant anda second frequency sampled at a second time instant and, a time intervalbetween the first and second time instants. In addition, the first timeinstant may occur after a first high frequency oscillator 114calibration and the second time instant may occur after a second highfrequency oscillator 114 calibration. Furthermore, the first timeinstant may occur after a first high frequency oscillator 114 clockadjustment which may occur after the first high frequency oscillator 114calibration.

The detected high frequency oscillator 114 frequency drift may beutilized to determine a time interval for adjusting the high frequencyoscillator 114 sleep time interval. In this regard, the determined timeinterval may be based on two or more high frequency oscillator 114calibrations and/or one or more high frequency oscillator 114 clockadjustments. The sleep time interval may be increased by adding a timedelay to an expected time to wake the high frequency oscillator 114and/or the high frequency oscillator 114 driven circuit 118. Also, thehigh frequency oscillator 114 and/or the high frequency oscillator 114driven circuit 118 sleep time interval may be decreased by subtracting atime interval from the expected wake time. According to an embodiment ofthe invention, the circuit 118 driven by the high frequency oscillator114 may be a radio circuit 118. The radio circuit 118 may be enabled toperform various tasks more quickly in instances when the time to wakethe high frequency oscillator 114 circuit is more accurate due to thetwo or more low frequency oscillator 110 calibrations between the highfrequency oscillator 114 sleep and wake cycles.

Another embodiment of the invention may provide a machine and/orcomputer readable storage and/or medium, having stored thereon, amachine code and/or a computer program having at least one code sectionexecutable by a machine and/or a computer, thereby causing the machineand/or computer to perform the steps as described herein for a methodand system for drift reduction in a low power oscillator (LPO) utilizedin a wireless communication device.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputer system or in a distributed fashion where different elements arespread across several interconnected computer systems. Any kind ofcomputer system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computer system with a computerprogram that, when being loaded and executed, controls the computersystem such that it carries out the methods described herein.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A method for signal processing, the method comprising: detecting afrequency drift of a low frequency oscillator; and adjusting a sleeptime interval for a circuit which is driven by a high frequencyoscillator, based on said detected frequency drift of said low frequencyoscillator.
 2. The method according to claim 1, the method comprisingadjusting a sleep time interval for said circuit while said highfrequency oscillator is driven by said low frequency oscillator.
 3. Themethod according to claim 1, comprising calibrating said low frequencyoscillator based on an output of said high frequency oscillator.
 4. Themethod according to claim 1, comprising detecting said frequency driftbased on a first frequency sampled at a first time instant and a secondfrequency sampled at a second time instant and a time interval betweensaid first time instant and said second time instant.
 5. The methodaccording to claim 4, wherein said first time instant occurs after afirst calibration of said low frequency oscillator and said second timeinstant occurs after a second calibration of said low frequencyoscillator.
 6. The method according to claim 5, wherein said first timeinstant occurs after a first low frequency oscillator clock adjustmentthat occurs after said first low frequency oscillator calibration. 7.The method according to claim 1, comprising determining a time intervalfor said adjusting said sleep time interval based on said detectedfrequency drift.
 8. The method according to claim 7, comprisingdetermining said time interval for said adjusting said sleep timeinterval based on two or more low frequency oscillator calibrationsand/or one or more low frequency oscillator clock adjustments.
 9. Themethod according to claim 8, comprising increasing said sleep timeinterval by adding a time delay to an expected time to wake said highfrequency oscillator.
 10. The method according to claim 8, comprisingdecreasing said sleep time interval by subtracting a time interval froman expected time to wake said high frequency oscillator.
 11. The methodaccording to claim 1, wherein said circuit driven by said high frequencyoscillator is a radio circuit.
 12. A system for signal processing, thesystem comprising: one or more circuits operable to detect a frequencydrift of a low frequency oscillator; and said one or more circuits areoperable to adjust a sleep time interval for a circuit which is drivenby a high frequency oscillator, based on said detected frequency driftof said low frequency oscillator.
 13. The system according to claim 12,wherein said one or more circuits enables adjustment of a sleep timeinterval for said circuit while said high frequency oscillator is drivenby said low frequency oscillator.
 14. The system according to claim 12,wherein said one or more circuits enables calibration of said lowfrequency oscillator based on an output of said high frequencyoscillator.
 15. The system according to claim 12, wherein said one ormore circuits enables detection of said frequency drift based on a firstfrequency sampled at a first time instant and a second frequency sampledat a second time instant and a time interval between said first timeinstant and said second time instant.
 16. The system according to claim15 wherein said first time instant occurs after a first calibration ofsaid low frequency oscillator and said second time instant occurs aftera second calibration of said low frequency oscillator.
 17. The systemaccording to claim 16, wherein said first time instant occurs after afirst low frequency oscillator clock adjustment that occurs after saidfirst low frequency oscillator calibration.
 18. The system according toclaim 12, wherein said one or more circuits enables determination of atime interval for said adjusting said sleep time interval based on saiddetected frequency drift.
 19. The system according to claim 18, whereinsaid one or more circuits enables determination of said time intervalfor said adjusting said sleep time interval based on two or more lowfrequency oscillator calibrations and/or one or more low frequencyoscillator clock adjustments.
 20. The system according to claim 19,wherein said one or more circuits enables an increase of said sleep timeinterval by adding a time delay to an expected time to wake said highfrequency oscillator.
 21. The system according to claim 19, wherein saidone or more circuits enables a decrease of said sleep time interval bysubtracting a time interval from an expected time to wake said highfrequency oscillator.
 22. The system according to claim 12, wherein saidcircuit driven by said high frequency oscillator is a radio circuit.